At present, the prior art provides some approaches for trying to meet the previously described needs. For example a first approach may be identified as Static Bit-mapping. Briefly, memory locations under failure are identified by reading the data stored in these memory locations, and by comparing this data with the expected values.
More particularly, this type of bitmapping allows downloading of the read data in a sequential way and comparing them with the expected values through an exclusive OR (EX-OR) operation at all the times that a memory location is accessed, and also if the read datum is equivalent to the expected one. In this case, the scanning BIST algorithm interrupts the scanning of the volatile memory while an external pin of the device is serially provided with the data compared in the EX-OR for comparison with the expected values.
This approach may be able to identify only static failures since the sequential access to the memory locations does not occur at the nominal working frequency, but is interrupted by the serial downloads. A second approach is Bitmapping on error. This second approach may be considered as a first in, first out (FIFO) structure for identifying the failure state.
According to this type of bitmapping, the read data may be serially downloaded only in case of a failure. Typically, there is a structure of FIFO registers with N stages to collect, at the same memory working speed and the nominal frequency, the failure states, and thus prevent the execution of the BIST algorithm of the RAM devices from being interrupted in case of consecutive multiple errors. The single stage of the FIFO structure is serially downloaded.
This architecture has the advantage of executing a bitmapping at the nominal frequency in case of consecutive failures and if the FIFO structure is not filled, i.e. in case an overflow in the FIFO structure does not occur. However, there are several drawbacks which limit the application of this diagnosis method.
For example, in case of filling of the FIFO structure, the failures detected are mixed (static/dynamic). In fact, when an overflow occurs, the sequential access to the memory is suspended until at least one register or stage of the FIFO structure is freed. Moreover, the tester should dynamically synchronize the download of the data since the failures are not deterministic, just like the flow of the data being output. Thus, it may be difficult to define the depth of the FIFO structure since a high number of registers or stages increases the occupied area even if it improves the possibility of executing a diagnosis at the same working speed of the memory device. In other words, if the FIFO structure is full, it may be impossible to detect failures of dynamic transitions.
The technical problem is that of providing a shared diagnosis method of the BIST algorithm for random access volatile memory devices having such features as to allow a dynamic bitmapping, overcoming, at the same time, the limits of the approaches already provided by the prior art.